In the fabrication of electronic devices, it is frequently necessary to provide a patterned layer of metallization, generally aluminum, which functions, for example, as an interconnection among devices on a substrate. Advances in fabrication techniques which have significantly reduced the size of individual devices on a substrate have sharply increased the density and complexity of devices in a given substrate area. The silicon substrate, or chip, has also increased in size to provide additional area for a larger number of devices.
Large integrated circuit chips containing many devices likewise contain an increased number of large areas of metallization such as, for example, bonding pads for circuit connections or metal circuit connector lines in excess of 10 micrometers in width. It is not uncommon for a chip to have forty or more such circuit connections. The package containing the chip must in turn have a like number of external connecting leads to the pads. The package is conventionally made of molded plastic or a ceramic material.
It is common practice to test packaged chips for both functional operation and reliability. Reliability testing generally includes both thermal shock and thermal cycle tests. In the latter, the packages are typically cycled between, e.g. -65.degree. and 150.degree.C. This causes both tensile and compression stresses to be applied to the chip due to mismatches in the thermal coefficient of expansion between the chip and the plastic package. These stresses often produce cracks in the insulating/passivating layer overlying such large areas of metallization, the chip itself or both. These stresses are particularly evident over a topographical feature on the substrate. During temperature stressing, the plastic package tends to move and to carry the topographical feature along. The stress produced will not affect the feature but may affect a line of metallization overlying it.
In addition to producing cracks in the insulator layer or the chip, these stresses can disturb the internal wire bonded contacts and can actually cause the metal pattern on the chip surface to move by a micrometer or more. Further, in the tightly packed geometry of very-large-scale-integrated circuits where there are overlying layers of metallization, the above-described stresses could cause a break in a glass insulator layer between them, resulting in a metal-to-metal short.
In the event that cracking occurs in the layer of passivating glass overlying a chip, the chip is no longer hermetically sealed. Failure may then occur because of corrosion due to moisture or excessive current leakage due to the presence of alkali metals. Experience has shown that passivation glass layers are most likely to crack where they overlie wide metallization lines such as those frequently found around the periphery of an integrated circuit chip. In accordance with this invention, a means has been found to substantially eliminate the above-described problems.